%FILES%
opt/
opt/intelFPGA/
opt/intelFPGA/24.1/
opt/intelFPGA/24.1/quartus/
opt/intelFPGA/24.1/quartus/common/
opt/intelFPGA/24.1/quartus/common/devinfo/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150b_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150b_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150b_vmbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_sc_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_sc_vmbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_vmbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_c7_gx150f_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_pmodel_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_h7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-8_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ff_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ff_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ff_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ff_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ff_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ff_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ii_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ii_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ii_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ii_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ii_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ii_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_pmodel_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-m_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ss_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ss_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ss_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ss_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ss_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-ss_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-tt_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-tt_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-tt_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-tt_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-tt_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150-tt_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_crosstalk.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_sc_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_sc_vmbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150fbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150fbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150fbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150mbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_d6_gtf150ufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150b_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150b_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150b_vmbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_sc_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_sc_vmbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_vmbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/ddb_cyclonev_e150f_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/zb16_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_d6_gtf150/zb8_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25b_vfbga256_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25b_vufbga324_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25f_sc_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25f_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25f_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e25f_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50b_vfbga256_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50b_vufbga324_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_h7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-8_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ff_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ff_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ff_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ff_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ff_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ff_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ii_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ii_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ii_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ii_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ii_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ii_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-m_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ss_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ss_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ss_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ss_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ss_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-ss_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-tt_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-tt_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-tt_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-tt_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-tt_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f-tt_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_crosstalk.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_sc_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50f_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50ffbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50fmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/ddb_cyclonev_e50fufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/zb16_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_e50f/zb8_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300b_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300b_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_sc_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_e300f_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_pmodel_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_h7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-8_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ff_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ff_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ff_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ff_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ff_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ff_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ii_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ii_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ii_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ii_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ii_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ii_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_pmodel_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-m_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ss_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ss_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ss_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ss_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ss_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-ss_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-tt_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-tt_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-tt_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-tt_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-tt_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f-tt_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_crosstalk.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_sc_vfbga1152_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_sc_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300f_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300ffbga1152_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300ffbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300ffbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300ffbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gt300fufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300b_vfbga1152_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300b_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300b_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_sc_vfbga1152_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_sc_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_vfbga1152_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/ddb_cyclonev_gx300f_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/zb16_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt300f/zb8_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75f_sc_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75f_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75f_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_e75f_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_h7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-8_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ff_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ff_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ff_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ff_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ff_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ff_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ii_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ii_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ii_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ii_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ii_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ii_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-m_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ss_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ss_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ss_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ss_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ss_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-ss_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-tt_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-tt_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-tt_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-tt_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-tt_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f-tt_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_crosstalk.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_sc_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_sc_vmbga301_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_sc_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75f_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75ffbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75ffbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75fmbga301_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75fmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gt75fufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50b_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_sc_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_sc_vmbga301_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_sc_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_vmbga301_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx50f_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75b_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_sc_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_sc_vmbga301_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_sc_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_vfbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_vmbga301_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_vmbga383_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/ddb_cyclonev_gx75f_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/zb16_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gt75f/zb8_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25b_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25b_vufbga324_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_h7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-8_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ff_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ff_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ff_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ff_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ff_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ff_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ii_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ii_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ii_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ii_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ii_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ii_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-m_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ss_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ss_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ss_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ss_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ss_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-ss_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-tt_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-tt_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-tt_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-tt_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-tt_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f-tt_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_sc_vfbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_sc_vufbga324_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25f_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25ffbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25fufbga324_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/ddb_cyclonev_gx25fufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/zb16_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_gx25f/zb8_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120b_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120b_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120b_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120b_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120b_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120bs_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120bs_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120bs_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120bs_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120bs_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120bs_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120bs_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120bs_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120m_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120m_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120m_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120m_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120m_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120m_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se120m_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90b_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90b_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90b_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90b_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90b_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90b_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90bs_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90bs_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90bs_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90bs_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90bs_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90bs_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90bs_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90bs_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90m_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90m_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90m_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90m_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90m_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90m_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_se90m_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st120f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st120f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st120f_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st120f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st120f_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st90f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st90f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st90f_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st90f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_st90f_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_pmodel_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_h7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-8_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ff_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ff_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ff_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ff_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ff_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ff_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ii_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ii_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ii_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ii_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ii_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ii_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_pmodel_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-m_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ss_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ss_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ss_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ss_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ss_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-ss_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-tt_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-tt_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-tt_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-tt_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-tt_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f-tt_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_crosstalk.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120f_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120ffbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx120fufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx90f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx90f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx90f_sc_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx90f_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx90f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx90f_vfbga896_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/ddb_cyclonev_sx90f_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/zb16_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx120f/zb8_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30b_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30b_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30b_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30b_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30bs_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30bs_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30bs_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30bs_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30bs_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30bs_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30bs_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30m_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30m_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30m_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30m_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se30m_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50b_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50b_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50b_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50b_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50b_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50b_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50b_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50bs_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50bs_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50bs_sc_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50bs_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50bs_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50bs_vufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50bs_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50m_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50m_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50m_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50m_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_se50m_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx30f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx30f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx30f_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx30f_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx30f_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h5_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h6_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_h7_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-8_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ff_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ff_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ff_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ff_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ff_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ff_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ii_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ii_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ii_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ii_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ii_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ii_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_rev_seu_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-m_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ss_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ss_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ss_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ss_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ss_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-ss_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-tt_revprod_1100mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-tt_revprod_1100mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-tt_revprod_1100mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-tt_revprod_1100mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-tt_revprod_1100mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f-tt_revprod_1100mv_n55c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_crosstalk.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_sc_v_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_sc_v_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_sc_vufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50f_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/ddb_cyclonev_sx50fufbga672_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/zb16_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/cyclonev_sx50f/zb8_mtm_cff_mapping.csv.enc
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_arm_meab.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_common_block.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_rev_seu_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_rev_seu_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_revprod_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_revprod_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h5_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_rev_seu_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_rev_seu_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_revprod_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_revprod_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_h6_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-6_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_100c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_125c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_100c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_125c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_n55c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h5_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_100c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_125c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_100c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_125c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_n55c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_h6_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_pmodel_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_pmodel_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_pmodel_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_pmodel_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_pmodel_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-7_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_rev_seu_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_rev_seu_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_revprod_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_revprod_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h6_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_rev_seu_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_rev_seu_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_revprod_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_revprod_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_h7_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-8_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ff_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ff_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ff_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ff_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ff_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ff_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ii_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ii_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ii_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ii_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ii_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ii_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_100c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_125c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_pmodel_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_100c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_125c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_rev_seu_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_100c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_125c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_n55c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-m_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ss_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ss_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ss_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ss_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ss_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-ss_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-tt_revprod_1100mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-tt_revprod_1100mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-tt_revprod_1100mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-tt_revprod_1100mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-tt_revprod_1100mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev-tt_revprod_1100mv_n55c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ff_0c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ff_100c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ff_125c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ff_85c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ff_n40c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ff_n55c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ii_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ii_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ii_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ii_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ii_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ii_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ss_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ss_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ss_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ss_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ss_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_ss_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_tt_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_tt_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_tt_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_tt_25c_nom.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_tt_85c_nom.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_tt_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_tt_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_aiot_tt_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_alm.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_cb_control-ss-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_clkbrst_lr-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_clkbrst_tb-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_clkmux_lr-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_clkmux_tb-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_dsp.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_altpe2_hip_top-ff1d18v-40c3scom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_altpe2_hip_top-ff1d18v125c3scom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_altpe2_hip_top-ss1d0v-40c1d25scom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_altpe2_hip_top-ss1d0v0c2d5scom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_altpe2_hip_top-tt1d1v85ccom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_smrt_smrtpack-ff1d18v-40c3scom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_smrt_smrtpack-ff1d18v125c3scom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_smrt_smrtpack-ss1d0v-40c1d25scom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_smrt_smrtpack-ss1d0v0c2d5scom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hd_smrt_smrtpack-tt1d1v85ccom_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hhp_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ff--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ff--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ff-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ff-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ff-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ff-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-int-tt--40-1-ss--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-int-tt--55-1-ss--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ss--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ss--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-tt--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-tt--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_3_c_if-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ff--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ff--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ff-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ff-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ff-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ff-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-int-tt--40-1-ss--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-int-tt--55-1-ss--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ss--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ss--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-tt--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-tt--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ff--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ff--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ff-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ff-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ff-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ff-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-int-tt--40-1-ss--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-int-tt--55-1-ss--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ss--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ss--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-tt--40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-tt--55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hi_6_c_if_gx75-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hm_hmc_32-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hm_hmc_32-ss-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hm_hmc_32-tt-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hm_hmc_32-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_hs_hps-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-int-tt-0-1_05-ss-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-int-tt-100-1_05-ss-100-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-int-tt-125-1_05-ss-125-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-int-tt-85-1_05-ss-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-int-tt-m40-1_05-ss-m40-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-int-tt-m55-1_05-ss-m55-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ss-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ss-100-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ss-125-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ss-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ss-m40-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-ss-m55-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-tt-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-tt-100-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-tt-125-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-tt-m40-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_im_sysclk-tt-m55-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_info_counts.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_group.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ff_0c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ff_100c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ff_125c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ff_85c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ff_n40c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ff_n55c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ii_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ii_100c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ii_125c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ii_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ii_n40c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ii_n55c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ss_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.ss_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.tt_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.tt_85c_nom.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_io_sim_cache.tt_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ioreg_sim_delays-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_c5-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_c5-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_c5-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_c5-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_c5-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_c5-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_c5-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_h_c5-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_h_c5-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_h_c5-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_h_c5-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_h_c5-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_h_c5-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_ioregdqs16_h_c5-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_lvl_top-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_mem_phy_32-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_mem_phy_32-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_mem_phy_32-ss-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_mem_phy_32-ss-125-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_mem_phy_32-ss-m40-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_mem_phy_32-tt-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ir_mem_phy_32-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_circuits.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ff_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ff_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ff_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ff_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ff_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ff_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ii_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ii_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ii_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ii_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ii_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ii_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_d6_gtf150fbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_d6_gtf150fbga672.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_d6_gtf150fbga896.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_d6_gtf150mbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_d6_gtf150ufbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_e50ffbga256.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_e50ffbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_e50fmbga383.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_e50fufbga324.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_e50fufbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt300ffbga1152.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt300ffbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt300ffbga672.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt300ffbga896.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt300fufbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt75ffbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt75ffbga672.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt75fmbga301.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt75fmbga383.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gt75fufbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gx25ffbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gx25fufbga324.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_gx25fufbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_sx120ffbga896.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_sx120fufbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_sx120fufbga672.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_sx50fufbga484.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_packages_cyclonev_sx50fufbga672.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ss_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ss_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ss_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ss_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ss_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_ss_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_tt_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_tt_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_tt_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_tt_25c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_tt_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_tt_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_jspice_tt_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_lab-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_la_mlab-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lab.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lei.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lut_ram.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_lutram_la_mlab-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mac.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-int-tt-0-1_05-ss-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-int-tt-100-1_05-ss-100-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-int-tt-125-1_05-ss-125-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-int-tt-85-1_05-ss-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-int-tt-m40-1_05-ss-m40-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-int-tt-m55-1_05-ss-m55-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ss-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ss-100-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ss-125-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ss-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ss-m40-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-ss-m55-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-tt-0-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-tt-100-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-tt-125-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-tt-m40-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mm_m10k-tt-m55-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_mtbf_constants.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_hps_phyclk_rt_bol-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_bl-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_r-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tl-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1455_phyclk_tr-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_r-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tl-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1456_phyclk_tr-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_r-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tl-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1457_phyclk_tr-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_r-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tl-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1458_phyclk_tr-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_bl-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_r-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tl-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1459_phyclk_tr-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1460_phyclk_rb-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pc_z1461_phyclk_rb_bol-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ff-0-1_21_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ff-100-1_21_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ff-125-1_21_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ff-85-1_21_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ff-m40-1_21_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ff-m55-1_21_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-int-tt-0-0_99-ss-0-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-int-tt-100-0_99-ss-100-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-int-tt-125-0_99-ss-125-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-int-tt-85-0_99-ss-85-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-int-tt-m40-0_99-ss-m40-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-int-tt-m55-0_99-ss-m55-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ss-0-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ss-100-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ss-125-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ss-85-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ss-m40-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-ss-m55-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-tt-0-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-tt-100-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-tt-125-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-tt-85-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-tt-m40-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pl_fpll_ip-tt-m55-0_99_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_deser-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_int-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ff-0-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ff-100-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ff-125-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ff-85-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ff-m40-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ff-m55-1_18_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-int-tt-0-1-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-int-tt-100-1-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-int-tt-125-1-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-int-tt-85-1-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-int-tt-m40-1-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-int-tt-m55-1-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ss-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ss-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ss-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ss-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ss-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-ss-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-tt-0-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-tt-100-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-tt-125-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-tt-85-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-tt-m40-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pm_ser-tt-m55-1_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_pwr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_qclkmux_co-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_qclkmux_lr-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_qclkmux_tb-tt-85-1_05_model.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_ram.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_rsi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonev_timing_corner_db.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonevc3_ip_to_ip_delays_tt_85c.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonevc5_ip_to_ip_delays_tt_85c.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonevc9_ip_to_ip_delays_tt_85c.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cyclonevd6_ip_to_ip_delays_tt_85c.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_cycloneve50_ip_to_ip_delays_tt_85c.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_hh120_ip_to_ip_delays_tt_85c.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_hh50_ip_to_ip_delays_tt_85c.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_tgx_lut_register.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_yeager_global_routing.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_yeager_local_routing.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclonev/ddb_yeager_ncfg.dxf
