%FILES%
opt/
opt/intelFPGA/
opt/intelFPGA/24.1/
opt/intelFPGA/24.1/quartus/
opt/intelFPGA/24.1/quartus/common/
opt/intelFPGA/24.1/quartus/common/devinfo/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_arm_meab.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_common_block.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cuda_clkbuf.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cuda_dsp.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cuda_io.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cuda_lab.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cuda_le.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cuda_pll.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-6_1200mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-6_1200mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-6_1200mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-6_1200mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_100c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_125c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1200mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_100c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_125c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_125c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-7_1_1200mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-8_1200mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-8_1200mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-8_1200mv_85c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-8_1200mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-8l_1000mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-8l_1000mv_100c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-8l_1000mv_85c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-8l_1000mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-m_1000mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-m_1000mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-m_1200mv_0c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-m_1200mv_0c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-m_1200mv_n40c_nlspccache.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp-m_1200mv_n40c_nlspcdata.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp.ref
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-6_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-6_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-6_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-6_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-7_1_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8l_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8l_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8l_1000mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8l_1000mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8l_1000mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8l_1000mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8l_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-8l_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-m_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-m_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-m_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-m_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-m_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-m_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-m_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1-m_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_e144i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_m164i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_u256i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_v1.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_v1_e144i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_v1_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_v1_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_v1_u256i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_v1fbga256_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_v1tqfp144_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1_v1ufbga256_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1fbga256_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1mbga164_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1tqfp144_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp1ufbga256_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-6_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-6_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-6_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-6_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-7_1_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8l_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8l_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8l_1000mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8l_1000mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8l_1000mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8l_1000mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8l_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-8l_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-m_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-m_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-m_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-m_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-m_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-m_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-m_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2-m_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-6_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-6_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-6_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-6_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-7_1_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8l_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8l_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8l_1000mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8l_1000mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8l_1000mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8l_1000mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8l_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-8l_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-m_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-m_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-m_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-m_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-m_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-m_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-m_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5-m_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_e144i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5_u256i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5fbga256_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5tqfp144_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_5ufbga256_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_e144i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_f484i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_m164i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_u256i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_u484i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_v1.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_v1_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_v1_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2_v1fbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2fbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2mbga164_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2tqfp144_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2ufbga256_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp2ufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-6_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-6_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-6_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-6_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-7_1_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8l_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8l_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8l_1000mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8l_1000mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8l_1000mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8l_1000mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8l_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-8l_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-m_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-m_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-m_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-m_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-m_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-m_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-m_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3-m_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_f484i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_u484i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_v1.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_v1_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_v1_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3_v1fbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3fbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp3ufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-6_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-6_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-6_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-6_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-7_1_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8l_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8l_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8l_1000mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8l_1000mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8l_1000mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8l_1000mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8l_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-8l_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-m_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-m_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-m_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-m_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-m_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-m_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-m_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4-m_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_f484i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4_u484i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4fbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp4ufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-6_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-6_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-6_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-6_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-7_1_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8l_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8l_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8l_1000mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8l_1000mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8l_1000mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8l_1000mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8l_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-8l_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-m_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-m_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-m_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-m_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-m_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-m_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-m_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5-m_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_f484i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_f780i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5_u484i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5fbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5fbga780_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp5ufbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_125c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_125c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-7_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8_1200mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8_1200mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8l_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8l_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8l_1000mv_100c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8l_1000mv_100c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8l_1000mv_85c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8l_1000mv_85c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8l_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-8l_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-m_1000mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-m_1000mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-m_1000mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-m_1000mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-m_1200mv_0c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-m_1200mv_0c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-m_1200mv_n40c.dmf.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6-m_1200mv_n40c_fdi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_asm.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_asmdb.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_asmdb_dirt.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_f484i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_f780i8lg_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_gid_database.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_icname.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_place.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_routing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6_timing.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6fbga484_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp6fbga780_pkg.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ff_1000mv_0c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ff_1000mv_n40c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ff_1000mv_n55c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ff_1200mv_0c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ff_1200mv_n40c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ff_1200mv_n55c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1000mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1000mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1000mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1000mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1000mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1000mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1200mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1200mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1200mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1200mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1200mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ii_1200mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1000mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1000mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1000mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1000mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1000mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1000mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1200mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1200mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1200mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1200mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1200mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_ss_1200mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1000mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1000mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1000mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1000mv_85c_nom.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1000mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1000mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1000mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1200mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1200mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1200mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1200mv_85c_nom.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1200mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1200mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_31um_tt_1200mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ff_1000mv_0c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ff_1000mv_n40c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ff_1000mv_n55c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ff_1200mv_0c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ff_1200mv_n40c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ff_1200mv_n55c_fast.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1000mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1000mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1000mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1000mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1000mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1000mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1200mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1200mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1200mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1200mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1200mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ii_1200mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1000mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1000mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1000mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1000mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1000mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1000mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1200mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1200mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1200mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1200mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1200mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_ss_1200mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1000mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1000mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1000mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1000mv_85c_nom.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1000mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1000mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1000mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1200mv_0c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1200mv_100c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1200mv_125c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1200mv_85c_nom.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1200mv_85c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1200mv_n40c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_aiot_45um_tt_1200mv_n55c_slow.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_bandwidth.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_basic.pll
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_blkrba.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_hdr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_info_counts.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ff_1000mv_0c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ff_1000mv_n40c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ff_1000mv_n55c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ff_1200mv_n40c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ff_1200mv_n55c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ii_1200mv_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ii_1200mv_100c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ii_1200mv_125c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ii_1200mv_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ii_1200mv_n40c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ii_1200mv_n55c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_tt_1000mv_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_tt_1000mv_85c_nom.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_tt_1000mv_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_tt_1200mv_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_tt_1200mv_85c_nom.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ff_1000mv_0c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ff_1000mv_n40c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ff_1000mv_n55c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ff_1200mv_n40c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ff_1200mv_n55c_fast.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ii_1200mv_100c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ii_1200mv_125c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ii_1200mv_n40c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ii_1200mv_n55c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_tt_1000mv_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_tt_1000mv_85c_nom.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_tt_1000mv_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_tt_1200mv_0c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_tt_1200mv_85c_nom.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_circuits.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ff_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ff_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ff_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ii_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ii_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ii_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ii_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ii_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ii_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ss_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ss_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ss_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ss_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ss_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_ss_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_tt_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_tt_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_tt_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_tt_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_tt_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_31um_tt_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_circuits.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ff_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ff_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ff_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ii_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ii_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ii_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ii_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ii_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ii_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ss_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ss_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ss_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ss_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ss_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_ss_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_tt_0c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_tt_100c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_tt_125c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_tt_85c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_tt_n40c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_45um_tt_n55c.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda1f17.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda2f17.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda2f23.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda2m8.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda2u19.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda3f17.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda4f19.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda4f23.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda4f29.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda4u19.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda5f23.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda5f29.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda6f23.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda6f29.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda7f23.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_jspice_packages_cuda7f29.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_lei.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_mtbf_constants.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_mtbf_constants_1000mv.sin
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_pad.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_part_info.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_pwr.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cyclone10lp_rsi.ddb
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cycloneii_dsp_ape.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_cycloneiii_ram.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_titan_io_group.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_yeager_global_routing.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_yeager_local_routing.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_yeager_ncfg.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_yeager_periph_blocks.dxf
opt/intelFPGA/24.1/quartus/common/devinfo/cyclone10lp/ddb_yeager_pll_block.dxf
